1. Field of the Invention
The invention relates to a method for fabricating a through hole, and more particularly, to a method for fabricating a through hole by performing two etching processes.
2. Description of the Prior Art
In semiconductor fabrication, in order to electrically connect device as metal oxide semiconductor (MOS) transistors with each metal conductive layer to form a complete electrical circuit, contact plugs and via plugs need to be formed in dielectric layers for serving as conductive lines of the MOS transistors and metal conductive layers when performing a multilevel metallization process.
The conventional process for forming contact plugs and via plugs includes performing an etching process to form through holes, such as contact holes and via holes, in the dielectric layers, and filling with metal materials with low resistivity into the contact holes and via holes to form the contact plugs and the via plugs. Since through hole manufacture affects the reliability of the electrical connection between two metal layers or conductive layers, it often becomes an important factor of the fabrication performance of the very large scale integration circuit.
Please refer to FIGS. 1–3. FIGS. 1–3 are schematic diagrams of a method for fabricating a through hole on a substrate 10 according to the prior art. As shown in FIG. 1, the substrate 10 comprises a conductive structure 12, wherein the conductive structure serves as a gate, a word line, a bit line, or a metal conductive line and comprises a metal conductive layer 14 and an anti-reflection coating (ARC) layer. According to the prior art, a dielectric layer 18 is formed on the surface of the substrate 10 at first. Then, as shown in FIG. 2, a patterned photoresist layer 20 is formed on the surface of the dielectric layer 18 to define at least a through hole above the conductive structure 12. Then, as shown in FIG. 3, an etching process is performed by taking the photoresist layer 20 as an etching mask to remove the dielectric layer 18 and the ARC layer 16 not covered by the photoresist layer 20 until the surface of the conductive layer 14 is exposed. Finally, the photoresist layer 20 is removed to accomplish the fabrication of the through hole 22.
Referring to FIG. 3, during the etching process using the photoresist layer 20 as the etching mask, the ARC layer 16 is etched in situ after the dielectric layer 18, which means the ARC layer 16 and the dielectric layer 18 are etched in the same reaction chamber. Generally, when the conductive layer 14 is composed of metal materials, such as alloy of Al and Cu, the ARC layer 16 will be composed of TiN, Ti, or the combination thereof, and the dielectric layer 18 will be composed of oxide. Therefore, CF4, CHF3, or other etching gases with high selectivity to oxide materials are chosen as the etching agent since the dielectric layer 18 is the primary etching object. However, the above-mentioned etching gases have low etching rates in the ARC layer 16 composed of TiN/Ti. Accordingly, the photoresist layer 20 serving as an etching mask is required to have a quite thick thickness to sustain a quite long time of the etching process until the ARC layer 16 is completely opened. During a longer etching process, corners being cut or collapse problem may possibly occur on the thicker photoresist layer 20. In addition, when the ARC layer 16 is being etched, the dielectric layer 18 positioned on the ARC layer 16 may be affected by the etching gas so that the through hole 22 will have an irregular sidewall. Furthermore, residues resulting from the removed ARC layer 16 may be formed on the sidewall of the dielectric layer 18 when etching the ARC layer 16, and such residues are hard to remove from the dielectric layer 18 so that the quality of the through hole 22 is degraded.